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STA382BWSTR 数据表(PDF) 91 Page - STMicroelectronics |
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STA382BWSTR 数据表(HTML) 91 Page - STMicroelectronics |
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91 / 172 page ![]() STA382BWS Register description: New Map Doc ID 022784 Rev 1 91/172 Figure 26. Short-circuit detection timing diagram (no short detected) In Figure 26 the short protection timing diagram is shown. The time information is expressed in clock cycles, where the clock frequency is defined as in section Section 6.13.1: Master clock select. The gray color is used for the short status bits to indicate that the bits are carrying the status of the previous EAPD 0->1 toggling (to be noted that after reset this state is meaningless since no EAPD transition occurs). The GND-related SHOK bits are updated as soon as the gnd test is completed, the VCC bits are updated after vcc test is completed, and the SOUT bit is updated after the shorted output test is completed. The gnd test, vcc test and output test, are always run (if the SHEN bit is active and EAPD toggled to ‘1’), and only if both tests are successful (no short) do the bridge outputs leave the tristate (indicated by dotted lines in the figure). If one of the three tests (or all) fail, the power bridge outputs are kept in the tristate until the procedure is restarted with a new EAPD toggling. In this figure EAPD is intended to be bit 7 of register 0x05. 6.29 Extended coefficient range up to -4...4 (address 0x5A) Biquads from 1 to 7 have in the STA382BWS the possibility to extend the coefficient range from [-1,1) to [-4..4) which allows the use of high-shelf filters that may require a coefficient dynamic greater in absolute value than 1. Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated. Each biquad has its independent setting according to the following table. EAPD OUT1A OUT1B OUT2A OUT2B GNDSH] VCCSH OUTSH] t s e t t r o h S f o d n E t s e t c c v t r a t S t s e t d n g t r a t S 44 cycles 50005 cycles 50005 cycles 1cycle Start out test TBD cycles D7 D6 D5 D4 D3 D2 D1 D0 CEXT_B4[1] CEXT_B4[0] CEXT_B3[1] CEXT_B3[0] CEXT_B2[1] CEXT_B2[0] CEXT_B1[1] CEXT_B1[0] 10 10 10 1 0 D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved CEXT_B7[1] CEXT_B7[0] CEXT_B6[1] CEXT_B6[0] CEXT_B51] CEXT_B5[0] 00 10 10 1 0 Obsolete Product(s) - Obsolete Product(s) |
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