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STA382BWSTR 数据表(PDF) 74 Page - STMicroelectronics

部件名 STA382BWSTR
功能描述  Sound Terminal 2.1-channel high-efficiency digital audio system
PDF  172 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA382BWSTR 数据表(HTML) 74 Page - STMicroelectronics

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Register description: New Map
STA382BWS
74/172
Doc ID 022784 Rev 1
6.23
Dynamic control registers (addr 0x23 - 0x26 / addr 0x43 -
0x46)
6.23.1
Limiter 1 attack/release rate (L1AR addr 0x23)
6.23.2
Limiter 1 attack/release threshold (L1ATRT addr 0x24)
6.23.3
Limiter 2 attack/release rate ( L2AR addr 0x25)
6.23.4
Limiter 2 attack/release threshold ( L2 ATRT addr 0x26)
The STA382BWS includes two independent limiter blocks. The purpose of the limiters is to
automatically reduce the dynamic range of a recording to prevent the outputs from clipping
in anticlipping mode or to actively reduce the dynamic range for a better listening
environment such as a nighttime listening mode which is often needed for DVDs. The two
modes are selected via the DRC bit in Section 6.11: FUNCT register (addr 0x0A). Each
channel can be mapped to either limiter or not mapped, meaning that the channel will clip
when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is
mapped to it, selects the maximum absolute value of all these channels, performs the
limiting algorithm on that value, and then, if needed, adjusts the gain of the mapped
channels in unison.
The limiter attack thresholds are determined by the LxAT registers if the EATHx[7] (bit D7 of
register 0x43 or 0x45) bits are set to 0, else the thresholds are determined by EATHx[6:0]. It
is recommended in anticlipping mode to set this to 0 dBfs, which corresponds to the
maximum unclipped output power of an FFX amplifier. Since gain can be added digitally
within the STA382BWS it is possible to exceed 0 dBfs or any other LxAT setting. When this
occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the
gain is reduced when the attack threshold is exceeded is dependent upon the attack rate
register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. Setting the
EATHx[7] bits to 1 selects the anticlipping mode.
The limiter release thresholds are determined by the LxRT registers if the ERTHx[7] (bit D7
of register 0x44 or 0x46) bits are set to 0, else the thresholds are determined by
D7
D6
D5
D4
D3
D2
D1
D0
L1A3
L1A2
L1A1
L1A0
L1R3
L1R2
L1R1
L1R0
01
10
10
1
0
D7
D6
D5
D4
D3
D2
D1
D0
L1AT3
L1AT2
L1AT1
L1AT0
L1RT3
L1RT2
L1RT1
L1RT0
01
10
10
0
1
D7
D6
D5
D4
D3
D2
D1
D0
L2A3
L2A2
L2A1
L2A0
L2R3
L2R2
L2R1
L2R0
01
10
10
1
0
D7
D6
D5
D4
D3
D2
D1
D0
L2AT3
L2AT2
L2AT1
L2AT0
L2RT3
L2RT2
L2RT1
L2RT0
01
10
10
0
1
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Product(s)
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