STA382BWSTR datasheet(92/172 Pages) STMICROELECTRONICS

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STA382BWS

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Doc ID 022784 Rev 1

Table 86.

Coefficients extended range configuration

In this case the user can decide, for each filter stage, the right coefficient range. Note that for

a given biquad the same range will be applied to the left and right (channel 1 and channel

2).

The crossover biquad does not have the availability of this feature, maintaining the [-1;1)

range unchanged.

6.30

Miscellaneous registers (address 0x5C, 0x5D)

6.30.1

Rate power-down enable (RPDNEN) bit

In the STA382BWS, by default, the power-down pin and I2C power-down act on mute

commands to perform the fade-out. This default can be changed so that the fade-out can be

started using the master volume. The RPDNEN bit, when set, activates this feature.

6.30.2

Bridge immediately off (BRIDGOFF) bit (address 0x4B, bit D5)

A fade-out procedure is started in the STA382BWS once the PWDN function is enabled, and

after 13 million clock cycles (PLL internal frequency) the bridge is put in power-down

(tristate mode). There is also the possibility to change this behavior so that the power bridge

will be switched off immediately after the PWDN pin is tied to ground, without waiting for the

13 million clock cycles. The BRIDGOFF bit, when set, activates this function. Obviously the

immediate power-down will generate a pop noise at the output, therefore this procedure

must be used only in cases where pop noise is not relevant in the application. Note that this

feature works only for hardware PWDN assertion and not for a power-down applied through

the IIC interface. Refer to Section 6.30.5 if programming a different number of clock cycles is

needed.

CEXT_Bx[1]

CEXT_Bx[0]

Range

[-1;1)

[-2;2)

[-4;4)

Reserved

RPDNEN

Reserved

BRIDGOFF

Reserved

CPWMEN

Reserved

LPDP

LPD

LPDE

PNDLSL[2]

PNDLSL[1]

PNDLSL[0]

Reserved

SHEN

Obsolete

Product(s)

- Obsolete

Product(s)

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