STA382BWSTR datasheet(66/172 Pages) STMICROELECTRONICS

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STA382BWS

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Doc ID 022784 Rev 1

6.17.3

PWM speed mode

6.17.4

Zero-crossing enable

The ZCE bit enables zero-crossing adjustment. When volume is adjusted on digital zero-

crossing, no clicks are audible

6.18

Configuration register F (addr 0x16)

6.18.1

Invalid input detect mute enable

Setting the IDE bit enables this function, which looks at the input I2S data and automatically

mutes if the signals are perceived as invalid.

6.18.2

Binary output mode clock loss detection

This bit detects loss of input MCLK in binary mode and will output 50% duty cycle.

Table 46.

PWM speed mode

Bit

R/W

RST

Name

Description

4R/W

PWMS

0: Normal speed (384 kHz) all channels

1: Odd speed (341.3 kHz) all channels. Not suitable for

binary BTL mode.

Table 47.

Zero-crossing enable

Bit

R/W

RST

Name

Description

6R/W

ZCE

‘1’: Volume adjustment only occurs at digital zero-crossing

‘0’: Volume adjustment occur immediately

EAPD

PWDN

ECLE

LDTE

BCLE

IDE

Reserved

Table 48.

Invalid input detect mute enable

Bit

R/W

RST

Name

Description

2R/W

IDE

Setting of 1 enables the automatic invalid input

detect mute

Table 49.

Binary output mode clock loss detection

Bit

R/W

RST

Name

Description

R/W

BCLE

Binary output mode clock loss detection enable

Obsolete

Product(s)

- Obsolete

Product(s)

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