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STA382BWSTR 数据表(PDF) 88 Page - STMicroelectronics

部件名 STA382BWSTR
功能描述  Sound Terminal 2.1-channel high-efficiency digital audio system
PDF  172 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA382BWSTR 数据表(HTML) 88 Page - STMicroelectronics

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Register description: New Map
STA382BWS
88/172
Doc ID 022784 Rev 1
6.27
PLL configuration registers (address 0x52; 0x53; 0x54; 0x55;
0x56; 0x57)
By default, the STA382BWS is able to configure the embedded PLL automatically
depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to
the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’)
The output PLL frequency formula is:
where Fin is the input clock frequency from the pad.
D7
D6
D5
D4
D3
D2
D1
D0
PLL_FRAC[15:8]
00
00
00
0
0
D7
D6
D5
D4
D3
D2
D1
D0
PLL_FRAC[7:0]
00
00
00
0
0
D7
D6
D5
D4
D3
D2
D1
D0
PLL_DITH[1:0]
PLL_NDIV[5:0]
00
00
00
0
0
D7
D6
D5
D4
D3
D2
D1
D0
PLL_DPD
PLL_FCT
PLL_STB
PLL_STBBYP
PLL_IDIV[3:0]
00
00
00
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
PLL_DIRP
PLL_PWD
PLL_BYP
OSC_PD
Reserved
BOOST32K
00
00
00
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
Reserved
Reserved
BYPSTATE
PDSTATE
OSCOK
LOWCK
NA
NA
NA
NA
NA
NA
NA
NA
Table 81.
PLL factors
PLL parameter
Min
Max
FRAC
0
65535
IDIV
0
3
NDIV
5
55
Fin
NDIV
()
IDIV
1
+
()
---------------------------
FRAC
65536
-----------------
⎝⎠
⎛⎞
+
⎝⎠
⎛⎞
×
Obsolete
Product(s)
- Obsolete
Product(s)



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