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STA382BWSTR 数据表(PDF) 101 Page - STMicroelectronics |
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STA382BWSTR 数据表(HTML) 101 Page - STMicroelectronics |
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101 / 172 page ![]() STA382BWS Register description: New Map Doc ID 022784 Rev 1 101/172 The STA382BWS implements an automatic CRC computation for the biquad and MDRC/XOver coefficient memory (Table 74). Memory cell contents from address 0x00 to 0x27 will be bit XORed to obtain the BQCHKE checksum, while cells from 0x28 to 0x31 will be XORed to obtain the XCCHKE checksum. Both checksums (24-bit wide) are exported on I2C registers from 0x60 to 0x65. The checksum computation will start as soon as the BCGO (for biquad RAM bank) or the XCGO bit (for MDRC/XOver coefficients) is set to 1. The checksum is computed at the processing sample rate if the IR bits equal “01” or “10”, otherwise the checksum is computed to half of the processing sample rate. When BCCMP or XCCMP is set to ‘1’, the relative checksum (BQCHKE and XCCHKE) is continuously compared with BQCHKR and XCCHKR respectively. If the checksum matches its own reference value, the respective result bits (BCRES and XCRES) will be set to ‘0’. The compare bits have no effect if the respective GO bit is not set. In case of checksum errors (i.e. the internally computed didn’t match the reference), an automatic device reset action can be activated. This function is enabled when the BCAUTO or XCAUTO bit is set to ‘1’. The automatic reset bits have no effect if the respective compare bits are not set. The recommended procedure for automatic reset activation is the following: ● Download the set of coefficients (RAM locations 0x00…0x27) ● Download the externally computed biquad checksum into registers BQCHKR ● Enable the checksum of the biquad coefficients by setting the BCGO bit. The checksum will start to be automatically computed by the STA382BWS and its value exposed on registers BQCHECKE. The checksum value is computed and updated. ● Enable the checksum comparison by setting the BCCMP bit. The internally computed checksum will start to be compared with the reference one and the result will be exposed on the BCRES bit. The following operation will be executed on each audio frame: if ((BQCHKE == BQCHKR)) { BC_RES = 0;// Checksum is ok, reset the error bit } 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 XCAUTO XCRES XCCMP XCGO BCAUTO BCCRES BCCMP BCCGO 00 00 00 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Obsolete Product(s) - Obsolete Product(s) |
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