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STA382BWSTR 数据表(PDF) 107 Page - STMicroelectronics

部件名 STA382BWSTR
功能描述  Sound Terminal 2.1-channel high-efficiency digital audio system
PDF  172 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA382BWSTR 数据表(HTML) 107 Page - STMicroelectronics

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STA382BWS
Register description: Sound Terminal compatibility
Doc ID 022784 Rev 1
107/172
7.1
Configuration register A (addr 0x00)
7.1.1
Master clock select
The STA382BWS supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin or BICKI pin (depending on MCS
settings) must be a multiple of the input sampling frequency (fs).
The relationship between the input clock (either XTI or BICKI) and the input sampling rate is
determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine
the PLL factor generating the internal clock and the IR bit determines the oversampling ratio
used internally. In Table 103 MCS 111 and 110 indicate that BICKI has to be used as the
clock source, while XTI is used in all the other cases.
Note:
(*) Clock is BICKI
D7
D6
D5
D4
D3
D2
D1
D0
FDRB
Reserved
Reserved
IR1
IR0
MCS2
MCS1
MCS0
01
10
01
1
1
Table 102.
Master clock select
Bit
R/W
RST
Name
Description
0R/W
1
MCS0
Selects the ratio between the input I2S sampling
frequency and the input clock.
1R/W
1
MCS1
2R/W
1
MCS2
Table 103.
Input sampling rates
Input
sampling rate
fs (kHz)
IR
MCS[2:0]
111
110
101
100
011
010
001
000
32, 44.1, 48
00
64*fs(*)
NA
576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs
88.2, 96
01
64*fs(*) 32*fs(*)
NA
64 * fs
128 * fs 192 * fs 256 * fs 384 * fs
176.4, 192
1X
64*fs(*) 32*fs(*)
NA
32 * fs
64 * fs
96 * fs
128 * fs 192 * fs
Obsolete
Product(s)
- Obsolete
Product(s)



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