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STA382BWSTR 数据表(PDF) 116 Page - STMicroelectronics |
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STA382BWSTR 数据表(HTML) 116 Page - STMicroelectronics |
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116 / 172 page ![]() Register description: Sound Terminal compatibility STA382BWS 116/172 Doc ID 022784 Rev 1 7.6 Configuration register F (addr 0x05) 7.6.1 Output configuration Note: To the left of the arrow is the processing channel. When using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs. D7 D6 D5 D4 D3 D2 D1 D0 EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0 01 01 11 0 0 Table 125. Output configuration Bit R/W RST Name Description 0 R/W 0 OCFG0 Selects the output configuration 1 R/W 0 OCFG1 Table 126. Output configuration engine selection OCFG[1:0] Output configuration PBTL enable 00 2-channel (full-bridge) power, 2-channel data-out: 1A/1B → 1A/1B 2A/2B → 2A/2B LineOut1 → 3A/3B LineOut2 → 4A/4B Line Out configuration determined by LOC register No 01 2(half-bridge).1(full-bridge) on-board power: 1A → 1A Binary 0 ° 2A → 1B Binary 90° 3A/3B → 2A/2B Binary 45° 1A/B → 3A/B Binary 0° 2A/B → 4A/B Binary 90° No 10 2-channel (full-bridge) power, 1-channel FFX: 1A/1B → 1A/1B 2A/2B → 2A/2B 3A/3B → 3A/3B EAPDEXT and TWARNEXT active No 11 1-channel mono-parallel: 3A → 1A/1B w/ C3BO 45° 3B → 2A/2B w/ C3BO 45° 1A/1B → 3A/3B 2A/2B → 4A/4B Yes Obsolete Product(s) - Obsolete Product(s) |
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