D950-CORE datasheet(76/89 Pages) STMICROELECTRONICS

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D950-Core

ISPR Interrupt Stack Pointer Register

ISPR contains the number of stacked priority levels. If the ISPR value is directly written, the

SPLi/CPL values are modified. So the ICR register content is no longer significant but the

interrupt routine procedure is not affected. After reset, ISPR default value is 0.

ISPR:

Number of stacked priority levels (0, 1, 2 or 3)

Note:’-’ is RESERVED (read: 0, write: don't care)

ISR Interrupt Status Register

ISR contains the eight interrupt pending bits, each being associated to one ITRQi interrupt

input.

IPEi-bit is set when the interrupt request is recorded and is reset when the interrupt request is

acknowledged (ITACK falling edge).

An interrupt request will not be acknowledged when IPEi-bit is reset by direct register write.

An interrupt request will be generated whatever the state of ITRQi when IPEi-bit is set by a

direct register write.

When only some pending interrupt requests need to be acknowledged, the IPEi bits of the

other ITRQi interrupt inputs must be reset.

When none of the pending interrupt requests need to be acknowledged, the IPE-bit of CCR

When IMi-bit is set, the corresponding IPEi-bit is reset. After reset, ISR default value is 0.

IPEi:

Interrupt Pending bit

0: Reset when interrupt request is acknowledged (def.)

1: Set when interrupt request is recorded

Note:‘-’ is RESERVED (read: 0, write: don't care)

2 - 1 - 0

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ISPR

9876543210

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IPE7 IPE6 IPE5 IPE4 IPE3 IPE2 IPE1 IPE0

D950-CORE 数据表(PDF) 76 Page - STMicroelectronics