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D950-CORE 数据表(PDF) 23 Page - STMicroelectronics |
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D950-CORE 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 89 page  23/89 D950-Core 3: Bit reverse addressing (on X-memory space only) with post-increment This mode can be selected for AX0, AX1 (see RX0, RX1 bits of STA register). It generates the bit-reversed address for 2k point FFT implementation (Index value = 2k-1). 4: Indirect indexed addressing. The address of the operand is the sum of the con- tents of the address register (AXi, AYi, SPX or SPY) and the contents of the se- lected index register (IXi or IYi). This addition occurs before the operand is ac- cessed and therefore requires an extra instruction cycle. The contents of the se- lected address and index registers are unchanged. Figures 4.8 and 4.9 show the schematics for indirect addressing with and without post modification. Figure 4.8 Indirect Addressing with Post-Modification Figure 4.9 Indirect Indexed Addressing without Post-Modification register value address Memory - linear - bit-reverse - modulo + index reg. address reg. VR02017H register value address Memory - linear + index reg. address reg. VR02017G 5 |
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