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D950-CORE 数据表(PDF) 29 Page - STMicroelectronics

部件名 D950-CORE
功能描述  16-Bit Fixed Point Digital Signal Processor DSP Core
PDF  89 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

D950-CORE 数据表(HTML) 29 Page - STMicroelectronics

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D950-Core
4.3.6 Sequence control
The PC is incremented at every cycle when the program flow is linear. Non linear sequencing
occurs in the following cases:
•
JUMP instructions
•
CALL and RTS instructions (JUMP and CALL can be immediate or computed /
delayed or not / conditional or not)
•
CCR bit and PORT bit can be tested
•
Interrupts and RTI instruction.
•
Processing of automatic loops.
Extension of the program memory space to more than 64k x 16-bit, can be achieved by
including a memory-mapped program page register (PPR) into the D950-Core glue logic. This
register is read or written to by move instructions.
Due to the pipe-line of instruction execution, changing page by loading a value into PPR will
be effective at the time of execution of the following instruction, which is read in the current
page. This operation will work properly if no interrupt occurs between the PPR load and the
JMP.
To avoid the need to disable interrupts by software, before page change, a special memory
mapped register address has been defined for PPR at address 0x0062.Y. Whenever a write
with direct address or a POP with direct address is attempted at this address, execution of the
following instruction can not be interrupted.
4.3.7 Halting program execution
There are 4 ways to halt program execution: low power mode, stop mode, hold state and halt
state. These 4 methods are detailed in the figure below and discussed in this section.
Figure 4.12
Halting Program Execution
RUN
HALT
HOLD
STOP
LOW POWER
(CLKOUT OFF)
(CLKOUT ON)
HALTACK
HALTACK
STOP
instruction
INTERRUPT
INTERRUPT
LP
instruction
HOLD
HOLD
LP pin
asserted
EMULATION
RESOURCE SHARING
LOW POWER
(CORE / PERIPHERALS)
LOW POWER
(CORE ONLY)
H
A
R
D
W
A
R
E
S
O
F
T
W
A
R
E
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