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D950-CORE 数据表(PDF) 39 Page - STMicroelectronics |
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D950-CORE 数据表(HTML) 39 Page - STMicroelectronics |
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39 / 89 page  39/89 D950-Core Table 4.5 Direct Address Register Table Note: Memory mapping is described in the appendix (see Section 8) Register Name Function Location AX0 X address register ACU AX1 X address register ACU AY0 Y address register ACU AY1 Y address register ACU IX0 X index register ACU IX1 X index register ACU IX2 X index register ACU IX3 X index register ACU IY0 Y index register ACU IY1 Y index register ACU IY2 Y index register ACU IY3 Y index register ACU SPX Stack Pointer register ACU LS Loop Start register PCU LC Loop Count register PCU LE Loop End register PCU L0 DCU input left register (LSB) DCU L1 DCU input left register (MSB) DCU R0 DCU input right register (LSB) DCU R1 DCU input right register (MSB) DCU PL Product register (LSB) DCU PH Product register (MSB) DCU CCR Condition Code Register DCU STA Status register DCU A0L Accumulator 0 (LSB) DCU A0H Accumulator 0 (MSB) DCU A0E Accumulator 0 (Extension) DCU BSC Barrel Shifter Control register DCU A1L Accumulator 1 (LSB) DCU A1H Accumulator 1 (MSB) DCU A1E Accumulator 1 (Extension) DCU PSC Product Shift Control register DCU |
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