D950-CORE datasheet(79/89 Pages) STMICROELECTRONICS

79 / 89 page

79/89

D950-Core

7.4.3 Operation

The DMA controller interface contains four independent channels allowing data transfer on I-

memory space and simultaneous data transfer on X and Y-memory spaces. When requests

occur at the same time on different channels, to transfer data on the same bus, the requests

are concatenated to be acknowledged during the same transfer, according to the following

fixed priority (see table):

The DMA transfer is based on a DSP cycle stealing operation:

•

The DMA controller generates a ‘hold request’ to the AS-DSP.

•

The AS-DSP sends back a ‘hold acknowledge’ to the DMA controller and

enters the hold state (bus released).

•

The DMA controller, manages the transfer and enters its idle state at the end of

the transfer, until reception of a new DMA request. The ‘hold request’ signal is

removed.

The data transfer duration is n+2 cycles, split into:

•

One cycle inserted at the beginning of the transfer when bus controls are

released by the D950-Core, n cycles for the number of data words to be trans-

ferred.

•

Another cycle is inserted at the end of the transfer when bus controls are

released by the DMA controller.

Single or block data can be transferred. The ‘DMA request’ signal is well adapted to such data

transfers by being either edge (single) or level (block) sensitive. Nevertheless, data blocks can

be transferred one data at time using an edge sensitive request signal.

A double buffering mechanism is available to deal with data blocks requiring the allocation of

2N addresses for the transfer of a N data block.

An interrupt can be used to warn AS-DSP that a predefined number of data have been

transferred and are ready to be processed. Interrupt requests are sent from the DMA controller

to the interrupt controller. The selected channels must be edge sensitive and the user has to

define the proper priority.

There are two ways to connect the DMA and the interrupt controllers, depending on the state

on the DIP_ENA static pin:

•

DIP_ENA = 0, there are enough available interrupt sources in the interrupt

controller: connect each DMA channel interrupt request (DITi, active on falling

Table 7.1

DMA Controller Interface Priority Levels

Priority

Channel

Level

Highest

Lowest

D950-CORE 数据表(PDF) 79 Page - STMicroelectronics

D950-CORE 数据表(HTML) 79 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

数据表下载