CC115LRGPR datasheet(28/74 Pages) TI2

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CSn

XOSC Stable

XOSC and voltage regulator switched on

SRES

40 us

XOSC Stable

CSn

CC115L

SWRS105B – MAY 2011 – REVISED JUNE 2014

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5.10.1 Power-On Start-Up Sequence

When the power supply is turned on, the system must be reset. This is achieved by one of the two

sequences described below, that is, automatic power-on reset (POR) or manual reset. After the automatic

power-on reset or manual reset, it is also recommended to change the signal that is output on the GDO0

pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192. However, to

optimize performance in TX, an alternative GDO setting from the settings found in Table 5-12 should be

selected.

5.10.1.1 Automatic POR

A power-on reset circuit is included in the CC115L. The minimum requirements stated in Section 4.10

must be followed for the power-on reset to function properly. The internal power-up sequence is

completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low.

See Section 5.5.1 for more details on CHIP_RDYn.

When the CC115L reset is completed, the chip will be in the IDLE state and the crystal oscillator will be

running. If the chip has had sufficient time for the crystal oscillator to stabilize after the power-on-reset, the

SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is completed, the SO

pin will first go high, indicating that the crystal oscillator is not stabilized, before going low as shown in

Figure 5-10.

Figure 5-10. Power-On Reset with SRES

5.10.1.2 Manual Reset

The other global reset possibility on CC115L uses the SRES command strobe. By issuing this strobe, all

internal registers and states are set to the default, IDLE state. The manual power-up sequence is as

follows (see Figure 5-11):

•

Set SCLK = 1 and SI = 0.

•

Strobe CSn low / high.

•

Hold CSn low and then high for at least 40 µs relative to pulling CSn low

•

Pull CSn low and wait for SO to go low ( CHIP_RDYn).

•

Issue the SRES strobe on the SI line.

•

When SO goes low again, reset is complete and the chip is in the IDLE state.

XOSC and voltage regulator switched on

Figure 5-11. Power-On Reset with SRES

Detailed Description

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