CC115LRGPR datasheet(41/74 Pages) TI2

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CC115L

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SWRS105B – MAY 2011 – REVISED JUNE 2014

5.18 System Considerations and Guidelines

5.18.1 SRD Regulations

International regulations and national laws regulate the use of radio receivers and transmitters. Short

Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315 MHz, 433

MHz, 868 MHz, or 915 MHz frequency bands. The CC115L is specifically designed for such use with its

300–348 MHz, 387–464 MHz, and 779–928 MHz operating ranges. The most important regulations when

using the CC115L in the 315 MHz, 433 MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220

V2.3.1 (Europe) and FCC CFR47 Part 15 (USA).

For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz

frequency range it is recommended to use a 26-MHz crystal for frequencies below 869 MHz and a 27

MHz crystal for frequencies above 869 MHz.

Compliance with regulations is dependent on the complete system performance. It is the customer's

responsibility to ensure that the system complies with regulations.

5.18.2 Calibration in Multi-Channel Systems

CC115L is highly suited for multi-channel systems due to its agile frequency synthesizer and effective

communication interface.

Charge pump current, VCO current, and VCO capacitance array calibration data is required for each

frequency when implementing a multi-channel system. There are 3 ways of obtaining the calibration data

from the chip:

1. Calibration for every frequency change. The PLL calibration time is 712/724

μs (26 MHz crystal and

TEST0 = 0x09/0B, see Table 5-6). The blanking interval between each frequency hop is then 787/799

µs.

2. Perform all necessary calibration at startup and store the resulting FSCAL3, FSCAL2, and FSCAL1

found for each RF frequency to be used. The VCO current calibration value and the charge pump

current calibration value available in FSCAL2 and FSCAL3 respectively are not dependent on the RF

frequency, so the same value can therefore be used for all RF frequencies for these two registers.

Between each frequency hop, the calibration process can then be replaced by writing the FSCAL3,

FSCAL2 and FSCAL1 register values that corresponds to the next RF frequency. The PLL turn on time

is approximately 75 µs (see Table 5-5). The blanking interval between each frequency hop is then

approximately 75 µs.

3. Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge

pump calibration. After writing to FSCAL3[5:4], strobe STX with MCSM0.FS_AUTOCAL=1 for each

new frequency hop. That is, VCO current and VCO capacitance calibration is done, but not charge

pump current calibration. When charge pump current calibration is disabled the calibration time is

reduced from 712/724 µs to 145/157 µs (26 MHz crystal and TEST0 = 0x09/0B, see Table 5-6). The

blanking interval between each frequency hop is then 220/232 µs.

There is a trade off between blanking time and memory space needed for storing calibration data in non-

volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space

to store calibration values. This solution also requires that the supply voltage and temperature do not vary

much in order to have a robust solution. Solution 3) gives 567 µs smaller blanking interval than solution 1).

The recommended settings for TEST0.VCO_SEL_CAL_EN change with frequency. This means that one

should always use SmartRF Studio to get the correct settings for a specific frequency before doing a

calibration, regardless of which calibration method is being used.

NOTE

The content in the TEST0 register is not retained in SLEEP state, thus it is necessary to re-

write this register when returning from the SLEEP state.

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