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CC115LRGPR 数据表(PDF) 55 Page - Texas Instruments

部件名 CC115LRGPR
功能描述  CC115L Value Line Transmitter
PDF  74 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

CC115LRGPR 数据表(HTML) 55 Page - Texas Instruments

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CC115L
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SWRS105B – MAY 2011 – REVISED JUNE 2014
Table 5-47. 0x2C: TEST2 - Various Test Settings
Bit
Field Name
Reset
R/W
Description
Use setting from SmartRF Studio SWRC176
This register will be forced to 0x88 or 0x81 when it wakes up from
SLEEP mode, depending on the configuration of
FIFOTHR.ADC_RETENTION.
7:0
TEST2[7:0]
136 (0x88)
R/W
The value read from this register when waking up from SLEEP
always is the reset value (0x88) regardless of the
ADC_RETENTION setting. The inverting of some of the bits due to
the ADC_RETENTION setting is only seen INTERNALLY in the
analog part.
Table 5-48. 0x2D: TEST1 - Various Test Settings
Bit
Field Name
Reset
R/W
Description
7:0
TEST1[7:0]
49 (0x31)
R/W
Use setting from SmartRF Studio SWRC176
Table 5-49. 0x2E: TEST0 - Various Test Settings
Bit
Field Name
Reset
R/W
Description
7:2
TEST0[7:2]
2 (000010)
R/W
Use setting from SmartRF Studio SWRC176
1
VCO_SEL_CAL_EN
1
R/W
Enable VCO selection calibration stage when 1
0
TEST0[0]
1
R/W
Use setting from SmartRF Studio SWRC176
5.19.3 Status Register Details
Table 5-50. 0x30 (0xF0): PARTNUM - Chip ID
Bit
Field Name
Reset
R/W
Description
7:0
PARTNUM[7:0]
0 (0x00)
R
Chip part number
Table 5-51. 0x31 (0xF1): VERSION - Chip ID
Bit
Field Name
Reset
R/W
Description
7:0
VERSION[7:0]
25 (0x19)
R
Chip version number. Subject to change without notice.
Copyright © 2011–2014, Texas Instruments Incorporated
Detailed Description
55
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Product Folder Links: CC115L



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