CC115LRGPR datasheet(32/74 Pages) TI2

32 / 74 page

CC115L

SWRS105B – MAY 2011 – REVISED JUNE 2014

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5.11 TX FIFO

The CC115L contains a 64-byte TX FIFO for data to be transmitted and the SPI interface is used to write

to the TX FIFO (see Section 5.5.5 for more details). The FIFO controller will detect underflow in the TX

FIFO.

When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow. A TX FIFO

overflow will result in an error in the TX FIFO content.

The chip status byte that is available on the SO pin while transferring the SPI header and contains the fill

grade of the TX FIFO if the access is a write operation. Section 5.5.1 contains more details on this.

The number of bytes in the TX FIFO can be read from the status registers TXBYTES.NUM_TXBYTES.

The 4-bit FIFOTHR.FIFO_THR setting is used to program threshold points in the TX FIFO.

Table 5-7 lists the 16 FIFO_THR settings and the corresponding thresholds for the TX FIFO.

Table 5-7. FIFO_THR Settings and the Corresponding FIFO Thresholds

FIFO_THR

Bytes in TX FIFO

0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)

13 (1101)

14 (1110)

15 (1111)

A signal will assert when the number of bytes in the TX FIFO is equal to or higher than the programmed

threshold. This signal can be viewed on the GDO pins (see Table 5-12).

Figure 5-12 shows the number of bytes in the TX FIFO when the threshold signal toggles in the case of

FIFO_THR=13. Figure 5-13 shows the signal on the GDO pin as the TX FIFO is filled above the threshold,

and then drained below in the case of FIFO_THR=13.

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