CC115LRGPR datasheet(43/74 Pages) TI2

43 / 74 page

CC115L

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SWRS105B – MAY 2011 – REVISED JUNE 2014

5.19 Configuration Registers

The configuration of CC115L is done by programming 8-bit registers. The optimum configuration data

based on selected system parameters are most easily found by using the SmartRF Studio software

SWRC176. Complete descriptions of the registers are given in the following tables. After chip reset, all the

registers have default values as shown in the tables. The optimum register setting might differ from the

default value. After a reset, all registers that shall be different from the default value therefore needs to be

programmed through the SPI interface.

There are 9 command strobe registers, listed in Table 5-13. Accessing these registers will initiate the

change of an internal state or mode. There are 34 normal 8-bit configuration registers listed in Table 5-14

and SmartRF Studio SWRC176 will provide recommended settings for these registers (Addresses marked

as “Not Used” can be part of a burst access and one can write a dummy value to them. Addresses

marked as “Reserved” must be configured according to SmartRF Studio SWRC176).

There are also 5 status registers that are listed in Table 5-15. These registers, which are read-only,

contain information about the status of CC115L.

The TX FIFO is accessed through one 8-bit register. During the header byte transfer and while writing

data to a register or the TX FIFO, a status byte is returned on the SO line. This status byte is described in

Table 5-2.

Table 5-16 summarizes the SPI address space. The address to use is given by adding the base address

to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for

base addresses above and below 0x2F.

Table 5-13. Command Strobes

Address

Strobe Name

Description

0x30

SRES

Reset chip.

Enable and calibrate frequency synthesizer

0x31

SFSTXON

(if MCSM0.FS_AUTOCAL=1).

0x32

SXOFF

Turn off crystal oscillator.

Calibrate frequency synthesizer and turn it

off. SCAL can be strobed from IDLE mode

0x33

SCAL

without setting manual calibration mode (

MCSM0.FS_AUTOCAL=0)

0x34

Reserved

In IDLE state: Enable TX. Perform calibration

0x35

STX

first if MCSM0.FS_AUTOCAL=1.

0x36

SIDLE

Enter IDLE state

0x37 - 0x38

Reserved

Enter power down mode when CSn goes

0x39

SPWD

high.

0x3A

Reserved

Flush the TX FIFO buffer. Only issue SFTX

0x3B

SFTX

in IDLE or TXFIFO_UNDERFLOW states.

0x3C

Reserved

No operation. May be used to get access to

0x3D

SNOP

the chip status byte.

Detailed Description

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