CC115LRGPR datasheet(40/74 Pages) TI2

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CC115L

SWRS105B – MAY 2011 – REVISED JUNE 2014

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5.17 Asynchronous and Synchronous Serial Operation

Several features and modes of operation have been included in the CC115L to provide backward

compatibility with previous Chipcon products and other existing RF communication systems. For new

systems, it is recommended to use the built-in packet handling features, as they can give more robust

communication, significantly offload the microcontroller, and simplify software development.

5.17.1 Asynchronous Serial Operation

Asynchronous transfer is included in the CC115L for backward compatibility with systems that are already

using the asynchronous data transfer.

When asynchronous transfer is enabled, all packet handling support is disabled and it is not possible to

use Manchester encoding.

Asynchronous serial mode is enabled by setting PKTCTRL0.PKT_FORMAT to 3. Strobing STX will

configure the GDO0 pin as data input (TX data) regardless of the content of the IOCFG0 register. Data

output can be on GDO0, GDO1, or GDO2. This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG

and IOCFG2.GDO2_CFG fields.

The CC115L modulator samples the level of the asynchronous input 8 times faster than the programmed

data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be

less than one eighth of the programmed data rate.

5.17.2 Synchronous Serial Operation

Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. When using this mode, sync

detection should be disabled together with CRC calculation ( MDMCFG2.SYNC_MODE=000 and

PKTCTRL0.CRC_EN=0).

Infinite

packet

length

mode

should

used

(

PKTCTRL0.LENGTH_CONFIG=10b).

In synchronous serial mode, data is transferred on a two-wire serial interface. The CC115L provides a

clock that is used to set up new data on the data input line or sample data on the data output line. Data

input (TX data) is on the GDO0 pin. This pin will automatically be configured as an input when TX is

active. The TX latency is 8 bits.

The MCU must handle preamble and sync word insertion/detection in software, together with CRC

calculation and insertion.

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