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CC115LRGPR 数据表(PDF) 47 Page - Texas Instruments |
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CC115LRGPR 数据表(HTML) 47 Page - Texas Instruments |
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47 / 74 page  CC115L www.ti.com SWRS105B – MAY 2011 – REVISED JUNE 2014 Table 5-16. SPI Address Space (continued) Write Read Single Byte Burst Single Byte Burst +0x00 +0x40 +0x80 +0xC0 0x30 SRES SRES PARTNUM 0x31 SFSTXON SFSTXON VERSION 0x32 SXOFF SXOFF Reserved 0x33 SCAL SCAL Reserved 0x34 Not Used Reserved Reserved 0x35 STX STX MARCSTATE 0x36 SIDLE SIDLE Reserved 0x37 Reserved Reserved Reserved 0x38 Reserved Reserved PKTSTATUS 0x39 SPWD SPWD Reserved 0x3A Reserved Reserved TXBYTES 0x3B SFTX SFTX Reserved 0x3C Reserved Reserved Reserved 0x3D SNOP SNOP Reserved 0x3E PATABLE PATABLE PATABLE PATABLE 0x3F TX FIFO TX FIFO Reserved Reserved 5.19.1 Configuration Register Details - Registers with preserved values in SLEEP state Table 5-17. 0x00: IOCFG2 - GDO2 Output Pin Configuration Bit Field Name Reset R/W Description 7 R0 Not used 6 GDO2_INV 0 R/W Invert output, that is, select active low (1) / high (0) 5:0 GDO2_CFG[5:0] 41 (101001) R/W Default is CHP_RDYn (see Table 5-12). Table 5-18. 0x01: IOCFG1 - GDO1 Output Pin Configuration Bit Field Name Reset R/W Description Set high (1) or low (0) output drive strength on the GDO 7 GDO_DS 0 R/W pins. 6 GDO1_INV 0 R/W Invert output, that is, select active low (1) / high (0) 5:0 GDO1_CFG[5:0] 46 (101110) R/W Default is 3-state (see Table 5-12). Table 5-19. 0x02: IOCFG0 - GDO0 Output Pin Configuration Bit Field Name Reset R/W Description 7 0 R/W Use setting from SmartRF Studio 6 GDO0_INV 0 R/W Invert output, that is, select active low (1) / high (0) Default is CLK_XOSC/192 (see Table 5-12). 5:0 GDO0_CFG[5:0] 63 (0x3F) R/W It is recommended to disable the clock output in initialization, in order to optimize RF performance. Copyright © 2011–2014, Texas Instruments Incorporated Detailed Description 47 Submit Documentation Feedback Product Folder Links: CC115L |
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