SSM2602CPZ-R2 datasheet(30/32 Pages) AD

30 / 32 page

SSM2602

Rev. 0 | Page 30 of 32

ALC CONTROL 1, ADDRESS 0x10

Table 37. ALC Control 1 Register Bit Map

ALCSEL [1:0]

MAXGAIN [2:0]

ALCL [[3:0]

Table 38. Descriptions of ALC Control 1 Register Bits

Bit Name

Description

Settings

ALCSEL [1:0]

ALC select

00 = ALC disabled (default)

01 = ALC enabled on right channel only

10 = ALC enabled on left channel only

11 = ALC enabled on both channels

MAXGAIN [2:0]

PGA maximum gain

000 = −12 dB

001 = −6 dB

… 6 dB steps up to

111 = 30 dB (default)

ALCL [3:0]

ALC target level

0000 = −28.5 dBFS

0001 = −27 dBFS

…

1011 = −12 dBFS (default)

… 1.5 dB steps up to

1111 = −6 dBFS

ALC CONTROL 2, ADDRESS 0x11

Table 39. ALC Control 2 Register Bit Map

DCY [3:0]

ATK [3:0]

Table 40. Descriptions of ALC Control 2 Register Bits

Bit Name

Description

Settings

DCY [3:0]

Decay (release) time control

0000 = 24 ms

0001 = 48 ms

0010 = 96 ms

0011 = 192 ms (default)

… (Time doubles with every step)

1010 = 24.576 sec

ATK [3:0]

ALC attack time control

0000 = 6 ms

0001 = 12 ms

0010 = 24 ms (default)

… (Time doubles with every step)

1010 = 6.144 sec

SSM2602CPZ-R2 数据表(PDF) 30 Page - Analog Devices

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