SSM2602CPZ-R2 datasheet(22/32 Pages) AD

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SSM2602

Rev. 0 | Page 22 of 32

RIGHT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x01

Table 14. Right-Channel ADC Input Volume Register Bit Map

RLINBOTH

RINMUTE

RINVOL [5:0]

Table 15. Descriptions of Right-Channel ADC Input Volume Register Bits

Bit Name

Description

Settings

RLINBOTH

Right-to-left line input ADC data load control

0 = disable simultaneous loading of right-channel ADC data to left-

channel register (default)

1 = enable simultaneous loading of right-channel ADC data to left-

channel register

RINMUTE

Right-channel input mute

0 = disable mute

1 = enable mute on data path to ADC (default)

RINVOL [5:0]

Right-channel PGA volume control

00 0000 = −34.5 dB

… 1.5 dB step up

01 0111 = 0 dB (default)

… 1.5 dB step up

01 1111 = 12 dB

10 0000 = 13.5 dB

10 0001 = 15 dB

10 0010 = 16.5 dB

10 0011 = 18 dB

10 0100 = 19.5 dB

10 0101 = 21 dB

10 0110 = 22.5 dB

10 0111 = 24 dB

10 1000 = 25.5 dB

10 1001 = 27 dB

10 1010 = 28.5 dB

10 1011 = 30 dB

10 1100 = 31.5 dB

10 1101 = 33 dB

11 1111 to 10 1101 = 33 dB

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