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SSM2602CPZ-R2 数据表(PDF) 6 Page - Analog Devices

部件名 SSM2602CPZ-R2
功能描述  Low Power Audio Codec
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM2602CPZ-R2 数据表(HTML) 6 Page - Analog Devices

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SSM2602
Rev. 0 | Page 6 of 32
Table 5. Digital Audio Interface Slave Mode Timing
Limit
Parameter
tMIN
tMAX
Unit
Description
tDS
10
ns
PBDAT setup time from BCLK rising edge
tDH
10
ns
PBDAT hold time from BCLK rising edge
tLRSU
10
ns
RECLRC/PBLRC setup time to BCLK rising edge
tLRH
10
ns
RECLRC/PBLRC hold time to BCLK rising edge
tDD
30
ns
RECDAT propagation delay from BCLK falling edge (external
load of 70 pF)
tBCH
25
ns
BCLK pulse width high
tBCL
25
ns
BCLK pulse width low
tBCY
50
ns
BCLK cycle time
BCLK
PBLRC/
RECLRC
PBDAT
RECDAT
tBCL
tDS
tLRSU
tLRH
tBCH
tBCY
tDD
tDH
Figure 4. Digital Audio Interface Slave Mode Timing
Table 6. Digital Audio Interface Master Mode Timing
Limit
Parameter
tMIN
tMAX
Unit
Description
tDST
30
ns
PBDAT setup time to BCLK rising edge
tDHT
10
ns
PBDAT hold time to BCLK rising edge
tDL
10
ns
RECLRC/PBLRC propagation delay from BCLK falling edge
tDDA
10
ns
RECDAT propagation delay from BCLK falling edge
tBCLKR
10
ns
BCLK rising time (10 pF load)
tBCLKF
10
ns
BCLK falling time (10 pF load)
tBCLKDS
45:55:00
55:45:00
BCLK duty cycle (normal and USB mode)
BCLK
PBLRC/
RECLRC
PBDAT
RECDAT
tDDA
tDST
tDHT
tDL
Figure 5. Digital Audio Interface Master Mode Timing



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