SSM2602

Rev. 0 | Page 19 of 32

TYPICAL APPLICATION CIRCUITS

AVDD VMID AGND

DBVDD DGND DCVDD

HPVDD

PGND

MICBIAS

RHPOUT

ROUT

MICIN

DIGITAL

PROCESSOR

RLINEIN

MUX

ADC

LLINEIN

MUX

ADC

DAC

DAC

LOUT

LHPOUT

OSC

CLK GEN

XTO

CLKOUT

CONTROL INTERFACE

MODE CSB SDIN SCLK

DIGITAL AUDIO INTERFACE

PBDAT RECDAT BCLK PBLRC RECLRC

OUT

DAC

ADC

PWROFF

REF

MIC

LINE

OSC

CLKOUT

SIDETONE

BYPASS

SSM2602

SIDETONE

BYPASS

Figure 31. SSM2602 Power Management Functional Location Diagram (Control Register R6, Bit D0 to Bit D7)

Connection under chip

CSB

SDIN

SCLK

DACLRC

DACDAT

ADCDAT

ADCLRC

BCLK

+3.3V_VAA

+3.3V_VAA

+3,3V_VDD

J4

BNC

1

C12

1uF

R4

NC

+

C21

10uF

R12

100

C26

220PF

C13

1uF

+

C3

10uF

C5

220PF

C27

220PF

C14

220uF

R6

NC

L1

FB

C20

0.1uF

C7

22pF

C11

220PF

C15

220uF

R8

0

C1

1uF

R13

47K

U1

SSM2602KCPZ

24

23

21

22

9

8

10

11

7

25

26

27

28

1

2

17

16

13

14

6

20

L_LINE_IN

R_LINE_IN

MIC_BIAS

MIC_IN

PBLRC

PBDAT

RECDAT

RECLRC

BCLK

MODE

CSB

SDIN

SCLK

MCLK/XTI

POR/XTO

ROUT

LOUT

LHP_OUT

RHP_OUT

CLKOUT

VMID

R15

47K

C24

0.1uF

J5

BNC

1

C2

1uF

L2

FB

R9

47K

C10

1uF

R1

0

J2

R

1

+

C18

10uF

C4

220PF

C6

0.1uF

J7

MIC_IN

1

R7

680

C23

0.1uF

+

C22

10uF

R11

100

R2

NC

R10

47K

C8

22pF

R5

100K

C19

0.1uF

R14

47K

J6

PHONEJACK STEREO SW

1

2

3

4

5

Y1

12.288MHz

R3

0

+

C25

10uF

J1

L

1

SPI[0..2]

I2S[0..4]

Figure 32. SSM2602 Typical Application Circuit