Low Power Audio Codec

SSM2602

Rev. 0

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FEATURES

Stereo, 24-bit analog-to-digital and digital-to-analog converters

DAC SNR: 100 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V

ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V

Highly efficient headphone amplifier

Stereo line input and monaural microphone input

Low power

7 mW stereo playback (1.8 V/1.5 V supplies)

14 mW record and playback (1.8 V/1.5 V supplies)

Low supply voltages

Analog: 1.8 V to 3.6 V

Digital core: 1.5 V to 3.6 V

Digital I/O: 1.8 V to 3.6 V

256/384 oversampling rate in normal mode; 250/272 over-

sampling rate in USB mode

Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,

22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,

and 96 kHz

28-lead, 5 mm × 5 mm LFCSP (QFN) package

APPLICATIONS

Mobile phones

MP3 players

Portable gaming

Portable electronics

Educational toys

GENERAL DESCRIPTION

The SSM2602 is a low power, high quality stereo audio codec

for portable digital audio applications with one set of stereo

programmable gain amplifier (PGA) line inputs and one

monaural microphone input. It features two 24-bit analog-to-

digital converter (ADC) channels and two 24-bit digital-to-

analog (DAC) converter channels.

The SSM2602 can operate as a master or a slave. It supports

various master clock frequencies, including 12 MHz or 24 MHz

12.288 MHz and 24.576 MHz; and many common audio sampling

rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 24 kHz,

22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.

The SSM2602 can operate at power supplies as low as 1.8 V for

the analog circuitry and as low as 1.5 V for the digital circuitry.

The maximum voltage supply is 3.6 V for all supplies.

The SSM2602 software-programmable stereo output options

provide the user with many application possibilities because the

device can be used as a headphone driver or as a speaker driver.

Its volume control functions provide a large range of gain

control of the audio signal.

The SSM2602 is specified over the industrial temperature range

of −40°C to +85°C. It is available in a 28-lead, 5 mm × 5 mm

lead frame chip scale package (LFCSP).

FUNCTIONAL BLOCK DIAGRAM

AVDD VMID AGND

DBVDD DGND DCVDD

HPVDD PGND

MICBIAS

RHPOUT

ROUT

MICIN

DIGITAL

PROCESSOR

RLINEIN

MUX

ADC

LLINEIN

MUX

ADC

DAC

DAC

LOUT

LHPOUT

SIDETONE

BYPASS

SIDETONE

BYPASS

CLK

MCLK/

XTI

XTO CLKOUT

CONTROL INTERFACE

MODE CSB SDIN SCLK

DIGITAL AUDIO INTERFACE

PBDAT RECDAT BCLK PBLRC RECLRC

0dB/20dB/

40dB BOOST

–34.5dB TO +33dB,

1.5dB STEP

–34.5dB TO +33dB,

1.5dB STEP

–73dB TO +6dB,

1dB STEP

–73dB TO +6dB,

1dB STEP

6dB TO 15dB/MUTE 3dB STEP

6dB TO 15dB/MUTE 3dB STEP

SSM2602

Figure 1.