ADE7166 datasheet(110/144 Pages) AD

110 / 144 page

ADE7566/ADE7569/ADE7166/ADE7169

Rev. A | Page 110 of 144

Table 104. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88)

Bit

Address

Mnemonic

Default

Description

0x8F

TF1

Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware

when the program counter (PC) vectors to the interrupt service routine.

0x8E

TR1

Timer 1 Run Control Bit. Set by the user to turn on Timer/Counter 1. Cleared by the user to turn

off Timer/Counter 1.

0x8D

TF0

Timer 0 Overflow Flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware

when the PC vectors to the interrupt service routine.

0x8C

TR0

Timer 0 Run Control Bit. Set by the user to turn on Timer/Counter 0. Cleared by the user to turn

off Timer/Counter 0.

0x8B

IE11

External Interrupt 1 (INT1) Flag. Set by hardware by a falling edge or by a zero level applied

to the external interrupt pin, INT1, depending on the state of Bit IT1. Cleared by hardware when

the PC vectors to the interrupt service routine only if the interrupt was transition activated.

If level activated, the external requesting source controls the request flag rather than the

on-chip hardware.

0x8A

IT11

External Interrupt 1 (IE1) Trigger Type. Set by software to specify edge sensitive detection, that is, 1-

to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level.

0x89

IE01

External Interrupt 0 (INT0) Flag. Set by hardware by a falling edge or by a zero level being applied

to the external interrupt pin, INT0, depending on the state of Bit IT0. Cleared by hardware when

the PC vectors to the interrupt service routine only if the interrupt was transition activated. If

level activated, the external requesting source controls the request flag rather than the on-chip

hardware.

0x88

IT01

External Interrupt 0 (IE0) Trigger Type. Set by software to specify edge sensitive detection, that is, 1-to-

0 transition. Cleared by software to specify level sensitive detection, that is, zero level.

1 These bits are not used to control Timer/Counter 0 and Timer/Counter 1 but are instead used to control and monitor the external INT0 and INT1 interrupt pins.

Table 105. Timer/Counter 2 Control SFR (T2CON, 0xC8)

Bit

Address

Mnemonic

Default

Description

0xCF

TF2

Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either

RCLK = 1 or TCLK = 1. Cleared by user software.

0xCE

EXF2

Timer 2 External Flag. Set by hardware when either a capture or reload is caused by a negative

transition on T2EX pin and EXEN2 = 1. Cleared by user software.

0xCD

RCLK

Receive Clock Enable Bit. Set by the user to enable the serial port to use Timer 2 overflow pulses

for its receive clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable

Timer 1 overflow to be used for the receive clock.

0xCC

TCLK

Transmit Clock Enable Bit. Set by the user to enable the serial port to use Timer 2 overflow pulses

for its transmit clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable

Timer 1 overflow to be used for the transmit clock.

0xCB

EXEN2

Timer 2 External Enable Flag. Set by the user to enable a capture or reload to occur as a result of a

negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by the

user for Timer 2 to ignore events at T2EX.

0xCA

TR2

Timer 2 Start/Stop Control Bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2.

0xC9

C/T2

Timer 2 Timer or Counter Function Select Bit. Set by the user to select the counter function (input

from external T2 pin). Cleared by the user to select the timer function (input from on-chip core

clock).

0xC8

CAP2

Timer 2 Capture/Reload Select Bit. Set by the user to enable captures on negative transitions at

T2EX if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or negative

transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the

timer is forced to autoreload on Timer 2 overflow.

ADE7166 数据表(PDF) 110 Page - Analog Devices

ADE7166 数据表(HTML) 110 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载