ST7FOXK2 datasheet(111/226 Pages) STMICROELECTRONICS

111 / 226 page

ST7FOXF1, ST7FOXK1, ST7FOXK2

On-chip peripherals

111/226

Figure 52.

Lite timer 2 block diagram

10.3.3

Functional description

Timebase Counter 1

The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it

starts incrementing from 0 at a frequency of fOSC/32. An overflow event occurs when the

counter rolls over from F9h to 00h. If fOSC = 8 MHz, then the time period between two

counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the

LTCSR1 register.

When Counter 1 overflows, the TB1F bit is set by hardware and an interrupt request is

generated if the TB1IE bit is set. The TB1F bit is cleared by software reading the LTCSR1

Input Capture

The 8-bit Input Capture register is used to latch the free-running upcounter (Counter 1) 1

after a rising or falling edge is detected on the LTIC pin. When an Input Capture occurs, the

ICF bit is set and the LTICR register contains the counter 1 value. An interrupt is generated

if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.

The LTICR is a read-only register and always contains the data from the last Input Capture.

Input Capture is inhibited if the ICF bit is set.

LTCSR1

8-bit TIMEBASE

8-bit

fLTIMER

LTIC

fOSC/32

TB1F

TB1IE

ICF

ICIE

LTTB1 INTERRUPT REQUEST

LTIC INTERRUPT REQUEST

LTICR

INPUT CAPTURE

1 or 2 ms

Timebase

(@ 8 MHz

fOSC)

To 12-bit AT TImer

fLTIMER

LTCSR2

TB2F

TB2IE

LTTB2

8-bit TIMEBASE

8-bit AUTORELOAD

LTCNTR

LTARR

COUNTER 2

COUNTER 1

Interrupt request

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