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ST7FOXK2 数据表(PDF) 114 Page - STMicroelectronics |
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ST7FOXK2 数据表(HTML) 114 Page - STMicroelectronics |
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114 / 226 page  On-chip peripherals ST7FOXF1, ST7FOXK1, ST7FOXK2 114/226 10.3.5 Interrupts The TBxF and ICF interrupt events are connected to separate interrupt vectors (see Section 7: Interrupts). They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction). 10.3.6 Register description Lite Timer Control/Status register 2 (LTCSR2) Reset value: 0000 0000 (00h) Bits 7:2 = Reserved, must be kept cleared. Bit 1 = TB2IE Timebase 2 Interrupt enable bit This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled Bit 0 = TB2F Timebase 2 Interrupt flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred Table 40. Description of interrupt events Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Active Halt Exit from Halt Timebase 1 Event TB1F TB1IE Yes Yes No Timebase 2 Event TB2F TB2IE No IC Event ICF ICIE No 7 0 00 0000 TB2IE TB2F Read / Write |
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