PSD813F2 datasheet(63/110 Pages) STMICROELECTRONICS

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PSD8XX Family

PSD835G2

9.4.6 Port D – Functionality and Structure

Port D has four I/O pins. See Figure 27. Port D can be configured to program one more of

the following functions:

t MCU I/O Mode

t CPLD Input – direct input to CPLD, no Input Micro

⇔Cells

Port D pins can be configured in PSDsoft as input pins for other dedicated functions:

t PD0 – ALE, as address strobe input

t PD1 – CLKIN, as clock input to the Micro

⇔Cells Flip Flops and APD counter

t PD2 – CSI, as active low chip select input. A high input will disable the

Flash/SRAM and CSIOP.

t PD3 – as DBE input from 68HC912

9.4.7 Port E – Functionality and Structure

Port E can be configured to perform one or more of the following functions (see Figure 28):

t MCU I/O Mode

t In-System Programming – JTAG port can be enabled for programming/erase of the

PSD8XX device. (See Section 9.6 for more information on JTAG programming.)

t Open Drain – Port E pins can be configured in Open Drain Mode

t Battery Backup features – PE6 can be configured as a Battery Input (Vstby) pin.

PE7 can be configured as a Battery On Indicator output

pin, indicating when Vcc is less than Vbat.

t Latched Address Output – Provided latched address (A7-0) output

DATA OUT

REG.

READ MUX

CPLD - INPUT

DIR REG.

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT D PIN

DATA OUT

Figure 27. Port D Structure

The

PSD835G2

Functional

Blocks

(cont.)

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