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PSD813F2 数据表(PDF) 31 Page - STMicroelectronics |
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PSD813F2 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 110 page  PSD8XX Family PSD835G2 30 The PSD835G2 Functional Blocks (cont.) MAIN FLASH DPLD FLASH BOOT BLOCK SRAM RS0 CSBOOT0-3 FS0-7 CS CS CS OE OE RD PSEN OE Figure 7. 80C51 Memory Modes – Separate Space Mode MAIN FLASH DPLD FLASH BOOT BLOCK SRAM RS0 CSBOOT0-3 FS0-7 RD CS CS CS RD OE OE VM REG BIT 2 PSEN VM REG BIT 0 VM REG BIT 1 VM REG BIT 3 VM REG BIT 4 OE Figure 8. 80C51 Memory Mode – Combined Space Mode 9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces 9.1.3.2.1 Separate Space Modes Code memory space is separated from data memory space. For example, the PSEN signal is used to access the program code from the main Flash Memory, while the RD signal is used to access data from the secondary Flash memory, SRAM and I/O Ports. This configuration requires the VM register to be set to 0Ch. 9.1.3.2.2 . Combined Space Modes The program and data memory spaces are combined into one space that allows the main Flash Memory, secondary Flash memory, and SRAM to be accessed by either PSEN or RD. For example, to configure the main Flash memory in combined space mode, bits 2 and 4 of the VM register are set to “1”. 9.1.3.3 80C51XA Memory Map Example See Application Notes for examples. |
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