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PSD813F2 数据表(PDF) 92 Page - STMicroelectronics

部件名 PSD813F2
功能描述  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PSD813F2 数据表(HTML) 92 Page - STMicroelectronics

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PSD835G2
PSD8XX Family
91
-90
-12
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
tLVLX
ALE or AS Pulse Width
22
24
tAVLX
Address Setup Time
(Note 1)
7
9
ns
tLXAX
Address Hold Time
(Note 1)
8
10
ns
tAVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
15
18
ns
t SLWL
CS Valid to Leading Edge of WR
(Note 3)
15
18
ns
t DVWH
WR Data Setup Time
(Note 3)
40
45
ns
t WHDX
WR Data Hold Time
(Notes 3 and 7)
5
8
ns
t WLWH
WR Pulse Width
(Note 3)
40
45
ns
tWHAX1
Trailing Edge of WR to Address Invalid
(Note 3)
8
10
ns
tWHAX2
Trailing Edge of WR to DPLD Address
(Notes 3 and 6)
0
0
ns
Input Invalid
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
33
33
ns
tWLMV
WR Valid to Port Output Valid Using
Micro
⇔Cell Register Preset/Clear
(Notes 3 and 4)
65
70
ns
tDVMV
Data Valid to Port Output Valid
Using Micro
⇔Cell Register Preset/Clear
(Notes 3 and 5)
65
68
ns
tAVPV
Address Input Valid to Address
(Note 2)
30
35
ns
Output Delay
Write Timing (3.0 V to 3.6 V Versions)
NOTES: 1. Any input used to select an internal PSD835G2 function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E and DS signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
6. tWHAX2 is Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
7.
tWHDX is 11ns when writing to the Output Micro⇔Cell Registers AB and BC.
Microcontroller Interface – PSD835G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)



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