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PSD813F2 数据表(PDF) 79 Page - STMicroelectronics

部件名 PSD813F2
功能描述  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PSD813F2 数据表(HTML) 79 Page - STMicroelectronics

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-70
-90
Slew
PT
TURBO
Rate
Symbol
Parameter
Conditions
Min
Max
Min
Max
Aloc
OFF
(Note 1)
Unit
Maximum Frequency
External Feedback
1/(tS +t CO)
34.4
30.30
MHz
Maximum Frequency
fMAX
Internal Feedback
1/(tS +t CO–10)
52.6
43.48
MHz
(fCNT)
Maximum Frequency
Pipelined Data
1/(tCH +t CL)
83.3
50.00
MHz
tS
Input Setup Time
14
15
Add 2 Add 12
ns
tH
Input Hold Time
0
0
ns
tCH
Clock High Time
Clock Input
6
10
ns
tCL
Clock Low Time
Clock Input
6
10
ns
tCO
Clock to Output Delay
Clock Input
15
18
Sub 2
ns
tARD
GPLD Array Delay
Any Micro
⇔Cell
11
16
Add 2
ns
tMIN
Minimum Clock Period
tCH +t CL (Note 2)
12
20
ns
GPLD Micro
⇔Cell Synchronous Clock Mode Timing (5 V ± 10% Versions)
NOTES: 1.
Fast Slew Rate output available on Port C and F.
2.
CLKIN tCLCL = tCH + tCL.
-70
-90
Slew
PT
TURBO
Rate
Symbol
Parameter
Conditions
Min
Max
Min
Max
Aloc
OFF
(Note 1)
Unit
tPD
GPLD Input Pin/Feedback to
20
25
Add 2 Add 12 Sub 2
ns
GPLD Combinatorial Output
tEA
GPLD Input to GPLD
Output Enable
21
26
Add 12 Sub 2
ns
tER
GPLD Input to GPLD
Output Disable
21
26
Add 12 Sub 2
ns
tARP
GPLD Register Clear or
Preset Delay
21
26
Add 12 Sub 2
ns
tARPW
GPLD Register Clear or
10
20
Add 12
ns
Preset Pulse Width
tARD
GPLD Array Delay
Any
11
16
Add 2
ns
Micro
⇔Cell
GPLD Combinatorial Timing (5 V ± 10%)
NOTE: 1. Fast Slew Rate output available on Port C and F.
PSD835G2 AC/DC Parameters – GPLD Timing Parameters
(5 V ± 10% Versions)
PSD8XX Family
PSD835G2
78



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