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PSD813F2 数据表(PDF) 12 Page - STMicroelectronics |
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PSD813F2 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 110 page  PSD835G2 PSD8XX Family 11 Table 6 shows the offset addresses to the PSD835G2 registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD835G2 registers. Table 6 provides brief descriptions of the registers in CSIOP space. For a more detailed description, refer to section 9. 7.0 PSD835G2 Register Description and Address Offset Register Name Port A Port B Port C Port D Port E Port F Port G Other* Description Data In 00 01 10 11 30 40 41 Reads Port pin as input, MCU I/O input mode Control 32 42 43 Selects mode between MCU I/O or Address Out Stores data for output Data Out 04 05 14 15 34 44 45 to Port pins, MCU I/O output mode Direction 06 07 16 17 36 46 47 Configures Port pin as input or output Configures Port pins as either CMOS or Open Drive Select 08 09 18 19 38 48 49 Drain on some pins, while selecting high slew rate on other pins. Input Micro ⇔Cell 0A 0B 1A Reads Input Micro ⇔Cells Reads the status of the Enable Out 0C 0D 1C 4C output enable to the I/O Port driver Read – reads output of Output Micro ⇔Cells A Micro ⇔Cells A 20 Write – loads Micro ⇔cell Flip-Flops Read – reads output of Output Micro ⇔Cells B Micro ⇔Cells B 21 Write – loads Micro ⇔cell Flip-Flops Mask 22 Blocks writing to the Micro ⇔Cells A Output Micro ⇔Cells A Mask 23 Blocks writing to the Micro ⇔Cells B Output Micro ⇔Cells B Flash Protection C0 Read only – Flash Sector Protection Flash Boot Read only – PSD Security Protection C2 and Flash Boot Sector Protection JTAG Enable C7 Enables JTAG Port PMMR0 B0 Power Management Register 0 PMMR2 B4 Power Management Register 2 Page E0 Page Register Places PSD memory VM E2 areas in Program and/or Data space on an individual basis. Memory_ID0 F0 Read only – Flash and SRAM size Memory_ID1 F1 Read only – Boot type and size Table 6. Register Address Offset |
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