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PSD813F2 数据表(PDF) 85 Page - STMicroelectronics |
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PSD813F2 数据表(HTML) 85 Page - STMicroelectronics |
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85 / 110 page  PSD8XX Family PSD835G2 84 Symbol Parameter Conditions Min Typ Max Unit tNLNH Warm RESET Active Low Time (Note 1) 150 ns tOPR RESET High to Operational Device 120 ns tNLNH-PO Power On Reset Active Low Time 1 ms tNLNH-A Warm RESET Active Low Time (Note 2) 25 µs Reset Pin Timing (5 V ± 10%) NOTE: 1. tCLCL is the CLKIN clock period. Microcontroller Interface – PSD835G2 AC/DC Parameters (5V ± 10% Versions) Symbol Parameter Conditions Min Typ Max Unit tBVBH Vstby Detection to Vstbyon Output High (Note 1) 20 µs tBXBL Vstby Off Detection to Vstbyon Output Low (Note 1) 20 µs Vstbyon Timing (5 V ± 10%) -70 -90 Symbol Parameter Conditions Min Max Min Max Unit tLVDV ALE Access Time from Power Down 80 90 ns Maximum Delay from APD Enable Using CLKIN Input 15 * tCLCL (µs) (Note 1) µs tCLWH to Internal PDN Valid Signal Power Down Timing (5 V ± 10%) NOTE: 1. RESET will not abort Flash programming/erase cycles. 2. RESET will abort Flash programming or erase cycle. NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms. |
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