 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
PSD813F2 数据表(PDF) 71 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
PSD813F2 数据表(HTML) 71 Page - STMicroelectronics |
|
|
71 / 110 page  PSD8XX Family PSD835G2 70 Port E Pin JTAG Signals Description PE0 TMS Mode Select PE1 TCK Clock PE2 TDI Serial Data In PE3 TDO Serial Data Out PE4 TSTAT Status PE5 TERR Error Flag Table 30. JTAG Port Signals 9.6 Programming In-Circuit using the JTAG-ISP Interface The JTAG-ISP interface on the PSD835G2 can be enabled on Port E (see Table 30). All memory (Flash and Flash Boot Block), PLD logic, and PSD configuration bits may be programmed through the JTAG-ISC interface. A blank part can be mounted on a printed circuit board and programmed using JTAG-ISP. The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and erase operations. *SR_cod and Periph Mode bits in the VM Register are always cleared to zero on power on or warm reset. ** Port Configuration Power On Reset Warm Reset Power Down Mode MCU I/O Input Mode Input Mode Unchanged PLD Output Valid after internal Valid Depend on inputs to PSD configuration PLD (address are bits are loaded blocked in PD mode) Address Out Tri-stated Tri-stated Not defined Data Port Tri-stated Tri-stated Tri-stated Peripheral I/O Tri-stated Tri-stated Tri-stated Table 29. Status During Power On Reset, Warm Reset and Power Down Mode Register Power On Reset Warm Reset Power Down Mode PMMR0, 2 Cleared to “0” Unchanged Unchanged Micro ⇔Cells Flip Cleared to “0” by Depend on .re and Depend on .re and Flop status internal power on .pr equations .pr equations reset VM Register* Initialized based on Initialized based on Unchanged the selection in the selection in PSDsoft PSDsoft Configuration Menu. Configuration Menu. All other registers Cleared to “0” Cleared to “0” Unchanged 9.5.3.4 Reset of Flash Erase and Programming Cycles An external reset on the RESET pin will also reset the internal Flash memory state machine. When the Flash is in programming or erase mode, the RESET pin will terminate the programming or erase operation and return the Flash back to read mode in tNLNH-A (minimum 25 µs) time. By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port E are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO. See ST Application Note AN1153 for more details on JTAG In-System-Programming. The PSD835G2 Functional Blocks (cont.) |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
