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PSD813F2 数据表(PDF) 89 Page - STMicroelectronics |
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PSD813F2 数据表(HTML) 89 Page - STMicroelectronics |
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89 / 110 page  PSD8XX Family PSD835G2 88 -90 -12 PT TURBO Slew Symbol Parameter Conditions Min Max Min Max Aloc OFF Rate Unit Maximum Frequency External Feedback 1/(tSA+t COA) 23.8 20.8 MHz Maximum Frequency fMAXA Internal Feedback ( fCNTA) 1/(tSA+t COA–10) 31.25 26.3 MHz Maximum Frequency Pipelined Data 1/(tCH A+t CLA) 38.4 30.3 MHz tSA Input Setup Time 8 10 Add 4 Add 20 ns tHA Input Hold Time 10 12 ns tCHA Clock High Time 15 18 Add 20 ns tCLA Clock Low Time 12 15 Add 20 ns tCOA Clock to Output Delay 34 38 Add 20 Sub 6 ns tARD GPLD Array Delay Any Micro ⇔Cell 23 27 Add 4 ns tMINA Minimum Clock Period 1/ fCNTA 32 38 ns GPLD Micro ⇔Cell Asynchronous Clock Mode Timing (3.0 V to 3.6 V Versions) NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. -90 -12 PT TURBO Symbol Parameter Conditions Min Max Min Max Aloc OFF Unit tIS Input Setup Time (Note 1) 0 0 ns tIH Input Hold Time (Note 1) 20 23 Add 20 ns tINH NIB Input High Time (Note 1) 13 13 ns tINL NIB Input Low Time (Note 1) 12 13 ns tINO NIB Input to Combinatorial Delay (Note 1) 46 62 Add 4 Add 20 ns Input Micro ⇔Cell Timing (3.0 V to 3.6 V Versions) PSD835G2 AC/DC Parameters – GPLD Timing Parameters (3.0 V to 3.6 V Versions) |
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