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数据搜索系统，热门电子元器件搜索 |
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PSD813F2 数据表(PDF) 80 Page - STMicroelectronics |
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PSD813F2 数据表(HTML) 80 Page - STMicroelectronics |
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80 / 110 page  PSD835G2 PSD8XX Family 79 PSD835G2 AC/DC Parameters – GPLD Timing Parameters (5 V ± 10% Versions) -70 -90 PT TURBO Slew Symbol Parameter Conditions Min Max Min Max Aloc OFF Rate Unit Maximum Frequency External Feedback 1/(tSA+t COA) 38.4 26.32 MHz Maximum Frequency fMAXA Internal Feedback 1/(tSA+t COA–10) 62.5 35.71 MHz (fCNTA) Maximum Frequency Pipelined Data 1/(tCH A+t CLA) 47.6 37.03 MHz tSA Input Setup Time 6 8 Add 2 Add 12 ns tHA Input Hold Time 7 12 ns tCHA Clock Input High Time 9 12 Add 12 ns tCLA Clock Input Low Time 12 15 Add 12 ns tCOA Clock to Output Delay 21 30 Add 12 Sub 2 ns tARDA GPLD Array Delay Any Micro ⇔Cell 11 16 Add 2 ns tMINA Minimum Clock Period 1/ fCNTA 16 28 ns GPLD Micro ⇔Cell Asynchronous Clock Mode Timing (5 V ± 10% Versions) -70 -90 PT TURBO Symbol Parameter Conditions Min Max Min Max Aloc OFF Unit tIS Input Setup Time (Note 1) 0 0 ns tIH Input Hold Time (Note 1) 15 20 Add 12 ns tINH NIB Input High Time (Note 1) 9 12 ns tINL NIB Input Low Time (Note 1) 9 12 ns tINO NIB Input to Combinatorial Delay (Note 1) 34 46 Add 2 Add 12 ns Input Micro ⇔Cell Timing (5 V ± 10% Versions) NOTE: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. |
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