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ST20-GP1 数据表(PDF) 8 Page - STMicroelectronics |
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ST20-GP1 数据表(HTML) 8 Page - STMicroelectronics |
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8 / 116 page ![]() ST20-GP1 8/116 ® Figure 2.1 ST20-GP1 architectural block diagram GPS radio 12 channel GPS Low controller power Real time clock 4K SRAM Programmable memory interface RAM ROM/ FLASH ST20-GP1 ST20 CPU Interrupt controller Serial communications Parallel input/output Byte-wide parallel port . 2 UART 1 OS-Link hardware DSP System services OS-Link Reset Analyse Error Clock 6 Interrupts User position output in ASCII . . 8 . . . |
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