ST20-GP1 datasheet(60/116 Pages) STMICROELECTRONICS

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ST20-GP1

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The behavior of the ST20-GP1 after reset depends upon the value on the BootSource0-1 pins. In

all cases, the EMI is loaded with a slow default conﬁguration which is suitable for performing

accesses to ROM and SRAM (see Figure 9.7).

Figure 9.7 Default conﬁguration

When booting from ROM, the ﬁrst EMI access will be an instruction fetch from bank 3. When

booting from a link, the bootstrap is loaded into the ST20-GP1 internal SRAM located logically at

the bottom of bank 0.

The default bus width for all banks is set at reset by reading the value on the BootSource0-1 pins

(see Table 9.1). If this bus width is inappropriate for a particular bank, then conﬁguration software

must change it before it is accessed, otherwise some memory locations will contain indeterminate

contents. Note, particular care must be paid to instruction fetching behavior of the CPU. It is

important to match the program memory with the correct bus width using BootSource0-1.

Parameter

Bits

Value during and after reset

Units

BusWidth

Depends on BootSource0-1 pins (see Table 9.1, page 52).

MemWaitEnable

1 (Enabled)

BankReadOnly

0 (Read/Write)

AccessDuration

1010 (10 cycles)

Cycles

CEe1Time

0000

Phases

CEe2Time

0000

Phases

OEe1Time

0000

Phases

WBe1Time

1001 (9 phases; 4.5 cycles)

Phases

WBe2Time

0010 (2 phases; 1 cycle)

Phases

BusReleaseTime

10 (2 cycles)

Cycles

DataDriveDelay

101 (5 phases; 2.5 cycles)

Phases

Table 9.9 Conﬁguration register values during reset

MemData0-15

(write)

MemAddr1-19

notMemCE

notMemOE

notMemWB0-1

MemData0-15

(read)

10 cycles

5 phases

2 cycles

2 phases (1 cycle)

9 phases (4.5 cycles)

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