ST20-GP1 datasheet(34/116 Pages) STMICROELECTRONICS

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ST20-GP1

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Instruction set

This chapter provides information on the instruction set. It contains tables listing all the instructions,

and where applicable provides details of the number of processor cycles taken by an instruction.

The instruction set has been designed for simple and efﬁcient compilation of high-level languages.

All instructions have the same format, designed to give a compact representation of the operations

occurring most frequently in programs.

Each instruction consists of a single byte divided into two 4-bit parts. The four most signiﬁcant bits

(MSB) of the byte are a function code and the four least signiﬁcant bits (LSB) are a data value, as

shown in Figure 6.1.

Figure 6.1 Instruction format

For further information on the instruction set refer to the

ST20 Instruction Set Manual (document

number 72-TRN-273-01).

6.1

Instruction cycles

Timing information is available for some instructions. However, it should be noted that many

instructions have ranges of timings which are data dependent.

Where included, timing information is based on the number of clock cycles assuming any memory

accesses are to 2 cycle internal memory and no other subsystem is using memory. Actual time will

be dependent on the speed of external memory and memory bus availability.

Note that the actual time can be increased by:

the instruction requiring a value on the register stack from the ﬁnal memory read in the pre-

vious instruction — the current instruction will stall until the value becomes available.

the ﬁrst memory operation in the current instruction can be delayed while a preceding

memory operation completes — any two memory operations can be in progress at any

time, any further operation will stall until the ﬁrst completes.

memory operations in current instructions can be delayed by access by instruction fetch or

subsystems to the memory interface.

there can be a delay between instructions while the instruction fetch unit fetches and par-

tially decodes the next instruction — this will be the case whenever an instruction causes

the instruction ﬂow to jump.

Note that the instruction timings given refer to ‘standard’ behavior and may be different if, for

example, traps are set by the instruction.

Function

Data

74 3

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