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ST20-GP1 数据表(PDF) 47 Page - STMicroelectronics |
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ST20-GP1 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 116 page  ST20-GP1 47/116 ® ADDRESS USE MEMORY BANK MaxInt #7FFFFFFF Bank 3 BootEntry #7FFFFFFE Boot entry point ↑ User code/Data/Stack and Boot ROM #40000000 ↑ RESERVED Bank 2 #2000E000 ↑ DSP controller peripheral (registers accessed via CPU device accesses) #2000C000 ↑ Parallel port controller peripheral (registers accessed via CPU device accesses) #2000A000 ↑ PIO controller peripheral (registers accessed via CPU device accesses) #20008000 ↑ ASC1 controller peripheral (registers accessed via CPU device accesses) #20006000 ↑ ASC0 controller peripheral (registers accessed via CPU device accesses) #20004000 ↑ EMI controller peripheral (registers accessed via CPU device accesses) #20002000 ↑ Interrupt and low power controller peripheral (registers accessed via CPU device accesses) #20000000 ↑ External peripherals or memory #00000000 ↑ User code/Data/Stack Bank 1 #C0000000 ↑ Bank 0 Start of external memory #80001000 ↑ MemStart #80000140 #80000130 Low priority Scheduler trapped process #80000120 Low priority Scheduler trap handler #80000110 Low priority SystemOperations trapped process #80000100 Low priority SystemOperations trap handler #800000F0 Low priority Error trapped process #800000E0 Low priority Error trap handler #800000D0 Low priority Breakpoint trapped process #800000C0 Low priority Breakpoint trap handler #800000B0 High priority Scheduler trapped process #800000A0 High priority Scheduler trap handler Figure 7.1 ST20-GP1 memory map |
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