ST20-GP1 datasheet(92/116 Pages) STMICROELECTRONICS

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ST20-GP1

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15.4.3 Direct DMA protocol

In this mode the PLink becomes an unsynchronized (i.e. direct action) bus. The PlinknotAck

output still behaves as if it were acknowledging a real transfer. The PlinknotReq signal has no

effect in this mode of operation. In this mode PlinknotAck is active high. The initial (inactive) state

of the pin is low.

Direct mode output

To drive the output pins the PLink must be programmed to make a single byte DMA. If more than

one byte is output, the PLink will continue to drive the output pins as fast as the output DMA can

feed the data, i.e. once every 8 or more system clock cycles, until the correct number of bytes have

been output. The sequence of events for a single byte read is outlined below. When conﬁgured as

an output the drivers are always driven.

The PLink forces the PlinknotAck pin high. The output pins are then driven with the new

data and the PlinknotAck pin is forced low.

The output data remains static and driven to the pads until either a new value is written as

output or until the link direction is changed. If the PLink returns to direct output mode, the

old data is once again driven to the pads.

Note: At reset PlinknotAck is a logic one, appearing to the outside world as an ‘acknowledge’.

External logic will assume that the data has been read. Therefore after programming the PLink to

direct mode the PlinknotAck output falls.

Direct mode input

To read the input pins the PLink must be programmed to make a single byte DMA. The sequence

of events for a single byte read is outlined below.

The PLink forces the PlinknotAck pin high. The input pins are then read and the Plinkno-

tAck pin is forced low.

Figure 15.3 Direct DMA protocol

ST20 Output

PlinknotAck

PlinkData0-7

ST20 Input

PlinknotAck

PlinkData0-7

valid data

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