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ST20-GP1 数据表(PDF) 82 Page - STMicroelectronics |
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ST20-GP1 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 116 page  ST20-GP1 82/116 ® ASCIntEnable register The ASCIntEnable register enables a source of interrupt. Interrupts will occur when a status bit in the ASCStatus register is 1, and the corresponding bit in the ASCIntEnable register is 1. ASCControl ASC base address + #0C Read/Write Bit Bit field Function 2:0 Mode ASC mode control Mode2:0 Mode 000 RESERVED 001 8-bit data 010 RESERVED 011 7-bit data + parity 100 9-bit data 101 8-bit data + wake up bit 110 RESERVED 111 8-bit data + parity 4:3 StopBits Number of stop bits selection StopBits1:0 Number of stop bits 00 0.5 stop bits 01 1 stop bit 10 1.5 stop bits 11 2 stop bits 5 ParityOdd Parity selection 0 Even parity (parity bit set on odd number of ‘1’s in data) 1 Odd parity (parity bit set on even number of ‘1’s in data) 6 LoopBack Loopback mode enable bit 0 Standard transmit/receive mode 1 Loopback mode enabled 7 Run Baud rate generator run bit 0 Baud rate generator disabled (ASC inactive) 1 Baud rate generator enabled 8 RxEnable Receiver enable bit 0 Receiver disabled 1 Receiver enabled 15:9 RESERVED. Write 0, will read back 0. Table 13.5 ASCControl register format |
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