ST20-GP1 datasheet(52/116 Pages) STMICROELECTRONICS

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ST20-GP1

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the initial bus width of all banks after reset.

9.2

Strobe allocation

9.3

External accesses

The EMI differentiates accesses and transactions. An access is the lowest denominator of a

transaction. Since the ST20 word size is 32 bits, several accesses are required to complete a

transaction in most cases. The following are cases where several accesses may not be required:

•

CPU executes a

sb (store byte), lb (load byte) or ss (store sixteen), ls (load sixteen) instruc-

tion.

•

CPU is executing a

move2dnonzero (2D block copy non-zero bytes) or move2dzero (2D

block copy zero bytes) instruction and the data dictates that certain bytes are not to be

written.

•

The ﬁrst or last DMA operation to or from a link is to a non word aligned byte address.

Figure 9.2 shows the generic EMI activity during a read access and the conﬁgurable parameters.

The rising edge of notMemOE always occurs at the end of the read access just after the data is

latched on chip. notMemWB0 is always inactive during a read access. notMemWB1 activity

during a read access depends on the bus width for the bank. The strobe is inactive if the bus width

is conﬁgured to be 16-bit. If the bus width is conﬁgured to be 8-bit, notMemWB1behaves as

address bit 0 with the same timing as MemAddr1-19.

BootSource[1:0] Bootstrap start-up conditions

Boot from link. 16-bit bus width for all banks.

Boot from ROM. 8-bit bus width for all banks. Link operational.

Boot from ROM. 16-bit bus width for all banks. Link powered down.

Boot from ROM. 8-bit bus width for all banks. Link powered down.

Table 9.1 BootSource0-1 encoding

Bank allocation

Correspondence

Active access type

notMemCE0-3

1 per bank

⇒ bank 0

⇒ bank 1

⇒ bank 2

⇒ bank 3

Reads and writes

notMemOE0-3

1 per bank

⇒ bank 0

⇒ bank 1

⇒ bank 2

⇒ bank 3

Reads only

notMemWB0

Shared amongst

all banks.

MemData0-7

Writes only. Indicates valid write data on MemData0-7.

notMemWB1

Shared amongst

all banks.

16-bit bus:

MemData8-15

Writes only. Indicates valid write data on MemData8-15.

8-bit bus:

not applicable

Reads and writes. Behaves as address bit 0 with same

timing as MemAddr1-19.

Table 9.2 Strobe allocation

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