ST20-GP1 datasheet(21/116 Pages) STMICROELECTRONICS

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ST20-GP1

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the last component, the counter is non zero and the component is descheduled. For the last

component, the counter is zero and the main process continues.

4.3

Priority

The following section describes ‘default’ behavior of the CPU and it should be noted that the user

can alter this behavior, for example, by disabling timeslicing and priority interrupts.

The processor can execute processes at one of two priority levels, one level for urgent (high

priority) processes, one for less urgent (low priority) processes. A high priority process will always

execute in preference to a low priority process if both are able to do so.

High priority processes are expected to execute for a short time. If one or more high priority

processes are active, then the ﬁrst on the queue is selected and executes until it has to wait for a

communication, a timer input, or until it completes processing.

If no process at high priority is active, but one or more processes at low priority are active, then one

is selected. Low priority processes are periodically timesliced to provide an even distribution of

processor time between computationally intensive tasks.

If there are

n low priority processes, then the maximum latency from the time at which a low priority

process becomes active to the time when it starts processing is the order of 2

n timeslice periods. It

is then able to execute for between one and two timeslice periods, less any time taken by high

priority processes. This assumes that no process monopolizes the CPU’s time; i.e. it has frequent

timeslicing points.

The speciﬁc condition for a high priority process to start execution is that the CPU is idle or running

at low priority and the high priority queue is non-empty.

If a high priority process becomes able to run whilst a low priority process is executing, the low

priority process is temporarily stopped and the high priority process is executed. The state of the

low priority process is saved into ‘shadow’ registers and the high priority process is executed.

When no further high priority processes are able to run, the state of the interrupted low priority

process is re-loaded from the shadow registers and the interrupted low priority process continues

executing. Instructions are provided on the processor core to allow a high priority process to store

the shadow registers to memory and to load them from memory. Instructions are also provided to

allow a process to exchange an alternative process queue for either priority process queue (see

Table 6.21 on page 43). These instructions allow extensions to be made to the scheduler for

custom runtime kernels.

A low priority process may be interrupted after it has completed execution of any instruction. In

addition, to minimize the time taken for an interrupting high priority process to start executing, the

potentially time consuming instructions are interruptible. Also some instructions are abortable and

are restarted when the process next becomes active (refer to the Instruction Set chapter).

4.4

Process communications

Communication between processes takes place over channels, and is implemented in hardware.

Communication is point-to-point, synchronized and unbuffered. As a result, a channel needs no

process queue, no message queue and no message buffer.

A channel between two processes executing on the same CPU is implemented by a single word in

memory; a channel between processes executing on different processors is implemented by point-

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