ST20-GP1 datasheet(24/116 Pages) STMICROELECTRONICS

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ST20-GP1

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Figure 4.4 Trap arrangement

There are four groups of traps, as detailed below.

•

Breakpoint

This group consists of the

Breakpoint trap. The breakpoint instruction (j0) calls the break-

point routine via the trap mechanism.

•

Errors

The traps in this group are

IntegerError and Overflow. Overflow represents arithmetic over-

ﬂow, such as arithmetic results which do not ﬁt in the result word.

IntegerError represents

errors caused when data is erroneous, for example when a range checking instruction ﬁnds

that data is out of range.

•

System operations

This group consists of the

LoadTrap, StoreTrap and IllegalOpcode traps. The IllegalOpcode

trap is signalled when an attempt is made to execute an illegal instruction. The

LoadTrap

and

StoreTrap traps allow a kernel to intercept attempts by a monitored process to change

or examine trap handlers or trapped process information. It enables a user program to sig-

nal to a kernel that it wishes to install a new trap handler.

•

Scheduler

The scheduler trap group consists of the

ExternalChannel, InternalChannel, Timer, TimeS-

lice, Run, Signal, ProcessInterrupt and QueueEmpty traps. The ProcessInterrupt trap sig-

nals that the machine has performed a priority interrupt from low to high. The

QueueEmpty

trap indicates that there is no further executable work to perform. The other traps in this

group indicate that the hardware scheduler wants to schedule a process on a process

queue, with the different traps enabling the different sources of this to be monitored.

The scheduler traps enable a software scheduler kernel to use the hardware scheduler to

implement a multi-priority software scheduler.

Note that scheduler traps are different from other traps as they are caused by the micro-

scheduler rather than by an executing process.

Note, when the scheduler trap is caused by a process that is ready to be scheduled, the

Wptr of that process is stored in the workspace of the scheduler trap handler, at address 0.

The trap handler can access this using a

ldl 0 instruction.

Low priority traps

High priority traps

Breakpoint

trap handler

CPU Error

trap handler

System operations

trap handler

Scheduler

trap handler

Breakpoint

trap handler

CPU Error

trap handler

System operations

trap handler

Scheduler

trap handler

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