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ST92141 - ANALOG TO DIGITAL CONVERTER (ADC)

7.6 ANALOG TO DIGITAL CONVERTER (ADC)

Important Note: This chapter is a generic descrip-

tion of the ADC peripheral. However depending on

the ST9 device, some or all of the interface signals

described may not be connected to external pins.

For the list of ADC pins present on the ST9 device,

refer to the device pinout description in the first

section of the data sheet.

7.6.1 Introduction

The Analog to Digital Converter (ADC) comprises

an input multiplex channel selector feeding a suc-

cessive approximation converter.

The conversion time depends on the INTCLK fre-

quency and the prescaler factor stored in the

PR[2:0] bits of the CRR register (R252).

The minimum conversion time is 138 INTCLK and

with the maximum prescaling factor it becomes

about 16 times longer.

For instance, with INTCLK at 20 MHz and PR[2:0]

equal to "111", conversion of the selected channel

requires 6.9µs.

It requires 27.45µs if PR[2:0]

equals "110" and so on. Refer to Table 30 for the

list of conversion and sampling times.

The 6.9µs time includes the 4

µs required by the

built-in Sample and Hold circuitry, which minimiz-

es the need for external components and allows

quick sampling of the signal to minimise warping

and conversion error.

Conversion resolution is 8 bits, with ±1 LSB maxi-

mum error in the input range between VSS and the

analog VDD reference.

The converter uses a fully differential analog input

configuration for the best noise immunity and pre-

cision performance. Two separate supply refer-

ences are provided to ensure the best possible

supply noise rejection. In fact, the converted digital

value, is referred to the analog reference voltage

which determines the full scale converted value.

Naturally

, Analog and Digital VSS MUST be com-

mon. If analog supplies are not present, input ref-

erence voltages are referred to the digital ground

and supply.

Up to 8 multiplexed Analog Inputs are available,

depending on the specific device type. A group of

signals can be converted sequentially by simply

programming the starting address of the first ana-

log channel to be converted and with the AUTO-

SCAN feature.

Two Analog Watchdogs are provided, allowing

continuous hardware monitoring of two input chan-

nels. An Interrupt request is generated whenever

the converted value of either of these two analog

inputs is outside the upper or lower programmed

threshold values. The comparison result is stored

in a dedicated register.

Figure 78. Block Diagram

INTERRUPT UNIT

INT. VECTOR POINTER

INT. CONTROL REGISTER

COMPARE RESULT REGISTER

THRESHOLD REGISTER

COMPARE LOGIC

DATA REGISTER 7

DATA REGISTER 6

DATA REGISTER 5

DATA REGISTER 4

DATA REGISTER 3

DATA REGISTER 2

DATA REGISTER 1

DATA REGISTER 0

SUCCESSIVE APPROXIMATION

A/D CONVERTER

ANALOG

MUX

AIN 7

AIN 6

AIN 5

AIN 4

AIN 3

AIN 2

AIN 1

AIN 0

CONVERSION

RESULT

AUTOSCAN LOGIC

CONTROL REG.

CONTROL

LOGIC

INTERNAL

TRIGGER

EXTERNAL

TRIGGER

VA00223

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