ST92141 datasheet(148/179 Pages) STMICROELECTRONICS

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ST92141 - ANALOG TO DIGITAL CONVERTER (ADC)

ANALOG TO DIGITAL CONVERTER (Cont’d)

Single and continuous conversion modes are

available. Conversion may be triggered by an ex-

ternal signal or, internally, by the Multifunction

Timer.

Conversion Time

The maximum conversion time is as follows:

138 * FDF * INTCLK

The minimum sample time is:

84 * FDF * INTCLK

where FDF is the Frequency Division Factor (refer

to the PR bit description in the CCR register).

For instance, if PR[2:0] = 100 -> FDF = 8

then the conversion time is:

138 * 8 * INTCLK = 1104 and the sample time is 84

* 8 * INTCLK = 672 INTCLK.

A Power-Down programmable bit allows the ADC

to be set in low-power idle mode.

The ADC’s Interrupt Unit provides two maskable

channels (Analog Watchdog and End of Conver-

sion) with hardware fixed priority, and up to 7 pro-

grammable priority levels.

CAUTION: ADC INPUT PIN CONFIGURATION

The input Analog channel is selected by using the

I/O pin Alternate Function setting (PXC2, PXC1,

PXC0 = 1,1,1) as described in the I/O ports sec-

tion. The I/O pin configuration of the port connect-

ed to the A/D converter is modified in order to pre-

vent the analog voltage present on the I/O pin from

causing high power dissipation across the input

buffer. Deselected analog channels should also be

maintained in Alternate function configuration for

the same reason.

7.6.2 Functional Description

7.6.2.1 Operating Modes

Two operating modes are available: Continuous

Mode and Single Mode. To enter one of these

modes it is necessary to program the CONT bit of

the Control Logic Register. The Continuous Mode

is selected when CONT is set, while Single Mode

is selected when CONT is reset.

Both modes operate in AUTOSCAN configuration,

allowing sequential conversion of the input chan-

nels. The number of analog inputs to be converted

may be set by software, by setting the number of

the first channel to be converted into the Control

sion is completed, the channel number is automat-

ically incremented, up to channel 7. For example,

if SC2, SC1, SC0 are set to 0,1,1, conversion will

proceed from channel 3 to channel 7, whereas, if

SC2, SC1, SC0 are set to 1,1,1, only channel 7 will

be converted.

When the ST bit of the Control Logic Register is

set, either by software or by hardware (by an inter-

nal or external synchronisation trigger signal), the

analog inputs are sequentially converted (from the

first selected channel up to channel 7) and the re-

sults are stored in the relevant Data Registers.

In Single Mode (CONT = “0”), the ST bit is reset

by hardware following conversion of channel 7; an

End of Conversion (ECV) interrupt request is is-

sued and the ADC waits for a new start event.

In Continuous Mode (CONT = “1”), a continuous

conversion flow is initiated by the start event.

When conversion of channel 7 is complete, con-

version of channel 's' is initiated (where 's' is spec-

ified by the setting of the SC2, SC1 and SC0 bits);

this will continue until the ST bit is reset by soft-

ware. In all cases, an ECV interrupt is issued each

time channel 7 conversion ends.

When channel 'i' is converted ('s' <'i' <7), the relat-

ed Data Register is reloaded with the new conver-

sion result and the previous value is lost. The End

of Conversion (ECV) interrupt service routine can

be used to save the current values before a new

conversion sequence (so as to create signal sam-

ple tables in the Register File or in Memory).

7.6.2.2 Triggering and Synchronisation

In both modes, conversion may be triggered by in-

ternal or external conditions; externally this may

be tied to EXTRG, as an Alternate Function input

on an I/O port pin, and internally, it may be tied to

INTRG, generated by a Multifunction Timer pe-

ripheral. Both external and internal events can be

separately masked by programming the EXTG/

INTG bits of the Control Logic Register (CLR). The

events are internally ORed, thus avoiding potential

hardware conflicts. However, the correct proce-

dure is to enable only one alternate synchronisa-

tion condition at any time.

The effect either of these synchronisation modes

is to set the ST bit by hardware. This bit is reset, in

Single Mode only, at the end of each group of con-

versions. In Continuous Mode, all trigger pulses

after the first are ignored.

The synchronisation sources must be at a logic

low level for at least the duration of one INTCLK

cycle and, in Single Mode, the period between trig-

ger pulses must be greater than the total time re-

quired for a group of conversions. If a trigger oc-

curs when the ST bit is still set, i.e. when conver-

sion is still in progress, it will be ignored.

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