C167CS-4RM datasheet(35/517 Pages) INFINEON

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C167CS

Derivatives

Architectural Overview

User’s Manual

2-18

V2.0, 2000-07

Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been

implemented to prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be

disabled in the time interval until the EINIT (end of initialization) instruction has been

executed. Thus, the chip’s start-up procedure is always monitored. The software has to

be designed to service the Watchdog Timer before it overflows. If, due to hardware or

software related failures, the software fails to do so, the Watchdog Timer overflows and

generates an internal hardware reset and pulls the RSTOUT pin low in order to allow

external hardware components to reset.

The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided by 2, 4, 128, or

256. The high byte of the Watchdog Timer register can be set to a prespecified reload

value (stored in WDTREL) in order to allow further variation of the monitored time interval.

Each time it is serviced by the application software, the high byte of the Watchdog Timer

is reloaded. Thus, time intervals between 21

µs and 671 ms can be monitored @

25 MHz (16

µs and 335 ms @ 33 MHz). The default Watchdog Timer interval after reset

is 5.2/4.0 ms (@ 25/33 MHz).

2.4

Power Management Features

The known basic power reduction modes (Idle and Power Down) are enhanced by a

number of additional power management features (see below). These features can be

combined to reduce the controller’s power consumption to the respective application’s

possible minimum.

• Flexible clock generation

• Flexible peripheral management (peripherals can be enabled/disabled separately or

in groups)

• Periodic wakeup from Idle mode via RTC timer

The listed features provide effective means to realize standby conditions for the system

with an optimum balance between power reduction (i.e. standby time) and peripheral

operation (i.e. system functionality).

Flexible Clock Generation

The flexible clock generation system combines a variety of improved mechanisms (partly

user controllable) to provide the C167CS modules with clock signals. This is especially

important in power sensitive modes like standby operation.

The power optimized oscillator generally reduces the amount of power which is

consumed in order to generate the clock signal within the C167CS.

The clock system efficiently controls the amount of power which is consumed in order

to distribute the clock signal within the C167CS.

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