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C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-2

V2.0, 2000-07

5.1

Interrupt System Structure

The C167CS provides 56 separate interrupt nodes that may be assigned to 16 priority

levels. In order to support modular and consistent software design techniques, most

sources of an interrupt or PEC request are supplied with a separate interrupt control

interrupt enable bit, and the interrupt priority of the associated source. Each source

request is then activated by one specific event, depending on the selected operating

mode of the respective device. For efficient usage of the resources also multi-source

interrupt nodes are incorporated. These nodes can be activated by several source

requests, e.g. as different kinds of errors in the serial interfaces. However, specific status

flags which identify the type of error are implemented in the serial channels’ control

registers.

The C167CS provides a vectored interrupt system. In this system specific vector

locations in the memory space are reserved for the reset, trap, and interrupt service

functions. Whenever a request occurs, the CPU branches to the location that is

associated with the respective interrupt source. This allows direct identification of the

source that caused the request. The only exceptions are the class B hardware traps,

which all share the same interrupt vector. The status flags in the Trap Flag Register

(TFR) can then be used to determine which exception caused the trap. For the special

software TRAP instruction, the vector address is specified by the operand field of the

instruction, which is a seven bit trap number.

The reserved vector locations build a jump table in the low end of the C167CS’s address

space (segment 0). The jump table is made up of the appropriate jump instructions that

transfer control to the interrupt or trap service routines, which may be located anywhere

within the address space. The entries of the jump table are located at the lowest

addresses in code segment 0 of the address space. Each entry occupies 2 words,

except for the reset vector and the hardware trap vectors, which occupy 4 or 8 words.

Table 5-1 lists all sources that are capable of requesting interrupt or PEC service in the

C167CS, the associated interrupt vectors, their locations and the associated trap

numbers. It also lists the mnemonics of the affected Interrupt Request flags and their

corresponding Interrupt Enable flags. The mnemonics are composed of a part that

specifies the respective source, followed by a part that specifies their function

(IR = Interrupt Request flag, IE = Interrupt Enable flag).

Note: Each entry of the interrupt vector table provides room for two word instructions or

one doubleword instruction. The respective vector location results from multiplying

the trap number by 4 (4 Bytes per entry).

All interrupt nodes that are currently not used by their associated modules or are

not connected to a module in the actual derivative may be used to generate

software controlled interrupt requests by setting the respective IR flag.

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